There are many structures
for thin-film transistors (TFTs), with the first major distinction among them
being planar CMOS structures vs. staggered amorphous-silicon (a-Si) structures.
Structure of TFT electrodes
The a-Si TFTs are further
divided into staggered and inverse-staggered types.
between top- and bottom-gate TFTs
In the inverse-staggered
type, the ohmic layer (n+ a-Si) in the channel region can either be etched
directly (the etch-back method) or etched by forming a protective film on
the a-Si thin film (the etch-stopper method).
Each method has its own set of advantages and disadvantages. The inverse-staggered
structure offers a relatively simple fabrication process and an electron mobility
that is about 30 percent larger than that of the staggered type. These advantages
have resulted in the bottom-gate TFT structure becoming more widely adopted
in TFT-LCD design, despite the fact that it's technically an upside-down structure.
Because a-Si has photoelectric
characteristics, the a-Si TFT must be shielded from incident light .The a-Si
layer must also be as thin as possible to minimize the generation of photo-induced
current, which can cause the TFT to malfunction.
Reduction of photo-induced
leakage current in a TFT
In the top-gate structure,
a light-shield layer must first be formed at the region of the TFT channel
The formation of this light shield may cause an extra process step. In bottom-gate
TFTs, on the other hand, a gate electrode is first formed at the TFT channel
region, where it also serves as a light-shield layer.
in a TFT-Array
Design Parameters for
The operational characteristics
of a TFT are determined by the sizes of its electrodes, the W/L ratio, and
the overlap between the gate electrode and the source-drain .
Design of an a-Si
The parasitic capacitances
resulting from the overlap of electrodes can not be avoided in staggered TFT
structures, but the parasitic effects must be minimized to maximize the LCD's
To reduce the overlap between the electrodes, a self-align process is often
capacitance in TFTs
It turns out that the characteristics
of the a-Si TFTs used in AMLCDs are very similar to the characteristics of
the MOSFETs in semiconductor devices.
of an a-Si TFT and its operating points
When a TFT panel is operated
under real-world conditions, the gate voltage is set at either 20 V for switch-on,
or at -5 V for switch-off. Under these operating conditions, the a-Si TFT
is a good switching device with an on/off current ratio larger than 106.
The performance of the TFT also depends on fabrication process parameters,
such as electron mobility and thickness of the gate insulators. If we wish
to increase the current gain of the TFT for better pixel-switching performance,
and the process parameters are fixed, the only thing we can do is increase
the W/L ratio. But doing this is not without a significant trade-off: The
larger W/L results in a lower aperture ratio - less of the pixel's area is
transparent to light when the pixel is ON - so the display's brightness and
contrast are reduced.
Storage Capacitor Design
To maintain a constant voltage
on a charged pixel over the entire frame cycle, a storage capacitor (Cs) is
fabricated at each pixel. A large Cs can improve the voltage holding ratio
of the pixel and reduce the kickback voltage, with resulting improvements
in contrast and flicker, but a large Cs results in a lower aperture ratio
and higher TFT load.
The storage capacitor can be formed by using either an independent storage-capacitor
electrode or part of the gate bus-line as a storage-capacitor electrode (Cs-on-gate
Example of an independent-Cs
design and equivalent circuit
Example of a Cs-on-gate
design and equivalent circuit
The advantages of the Cs-on-gate
method are that it eliminates the need for modification in the fabrication
process; it minimizes the number of processes; and it produces a larger aperture
ratio than does the independent Cs method. But few things are free in TFT-LCD
design. The trade-off with the Cs-on-gate method is an increase in the RC
time constant of the gate bus-line, which reduces the TFT switching performance.
This RC delay problem can
have serious effects on the appearance of the display.
RC delay of a gate
signal and its effect on a black display
The solution lies in fabricating
the gate bus-line with a low-resistance material such as aluminum (Al).
Signal Bus-line Design
The requirement that the
gate bus-line must have a small RC time delay is particularly important for
larger and higher-resolution LCDs. If the widths of the signal bus-lines are
increased to reduce resistance, the aperture ratio of the pixels is reduced,
so the preferred approach is to use a low-resistance material for the bus-lines.
For this, Al offers advantage over other metals, such as Cr, W, and Ta.
But, in the bottom-gate TFT process, the gate electrodes are first fabricated
on the glass substrate and then subjected to high-temperature processes and
various chemical etches. So, to use Al as a gate-electrode material, the Al
gate electrodes must be protected from damage produced by hillock formation.
Design of low-resistance
aluminum gate bus-line
A thin film of an aluminum
oxide (Al2O3), formed by anodic oxidation of the Al surface at room temperature,
can protect the Al electrodes from the problems associated with hillock formation.
Double-metal or clad structures over the Al electrodes - using a relatively
stable material such as Cr, Ta, or W - can also be used to protect the Al
electrodes. The trade-off is that these approaches require an additional process.
Recently, Al alloy (such as Al-Nd), which can suppress hillock formation,
has been used as a gate-electrode material to eliminate the additional process.
As implied previously, another
important design consideration is maximizing the aperture ratio of the pixel.
In the unit cell, TFT electrodes, storage-capacitor electrodes, signal bus-lines,
and the black-matrix material constitute opaque areas.
Opaque areas and aperture
ratio of a pixel
The combined areas of these
elements, along with the area of the pixel aperture through which light can
pass, determine the aperture ratio of the pixel. The aperture ratio is given
by the area of the pixel aperture divided by the total pixel area (aperture
area plus the area of the opaque elements). To increase the aperture ratio
as much as possible, the size of the opaque elements must be made as small
as possible, while maintaining a design that maximizes the size of the pixel-electrode
Unfortunately, one can only go so far in reducing the opaque areas before
degrading image quality and yield. As shown in Fig. 12, the light-shield area
on the color-filter substrate must be extended to block the light leaking
through the gap between the data-line and the pixel ITO. To do this in conventional
TFT-LCD cell structures, while simultaneously providing an adequate plate-alignment
margin, significantly reduces the aperture.
But far higher aperture
ratios can be achieved by switching from a conventional structure to the BM-on-Array
structure, regardless of the accuracy of the plate alignment. The aperture
ratio of this cell structure is not determined by the BM opening at the color
filter substrate, but by the BM-on-Array, which can be formed with a very
high positioning accuracy.
Improvement of aperture
ratio using a black-matrix-on-TFT-array
In an independent-Cs-electrode
design, the aperture ratio can be increased if the storage-capacitor electrode
is fabricated using ITO.
Improvement of aperture
ratio using an ITO layer as a Cs electrode
Design for Redundancy
Even when the greatest care
is taken and sophisticated quality-management procedures are applied, it is
not possible to make the TFT-array fabrication process so perfect that it
produces only completely defect-free arrays.
Possible line and
pixel defects on a TFT array
To improve the production
yield in the fabrication process, redundancy design, repairable design, and
fault-tolerant designs are often used. Dual-bus-line design or double-metal
structure can help recover from problems of line breakage. Dummy-repair-line
design can save the defective panel from data-bus-line open failures. While
these redundant-design techniques can effectively improve fabrication yield,
in some cases they can also reduce the aperture ratio.
The TFT-array must be protected
from electrostatic discharge (ESD), which can be generated in the fabrication
processes such as during the rubbing of the alignment layer and spin-drying.
Design approaches for protecting the TFT-array against ESD include bus-line
shorting and ESD protection circuits.
ESD protection using
a bus-line shorting method
ESD protection using
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